Savannah Riverwalk Walk 🚶‍♂️ | Ships, Riverboats & Waterfront Dining

Anna Ruby Falls Hike (Easy Waterfall Near Helen, GA)

Raven Cliffs Hike: Beautiful Waterfall Along the Trail

The Truth About Engineer Life (Road Trip Begins)

The Op-Amp Differentiator: Stability, Phase Margin, and Practical Design

The Op-Amp Integrator Circuit Explained | Ideal vs Practical Design

Understanding a Common Circuit Model Used for IC Pins

Simple Relaxation Oscillator Explained | Math + LTspice Simulation

Voltage Doubling with the Dickson Charge Pump (Math + LTspice)

How to Double a Voltage Using Capacitors (Switched-Capacitor Circuit)

Implementing CIC Filters in Vivado for Software-Defined Radio Applications

I Ran the Numbers on a Popular Etsy Product (It Wasn’t Worth It)

Simple Table Saw Sled Build (16” x 16”) | Accurate & Safer Cuts

You Control Less Than You Think—Except This

Low-Leverage Work Disguised as a Side Hustle

How I Lost 30 Pounds in 4 Months on the Mayo Clinic Diet

How FPGA Decimation FIR Filters Work in Software-Defined Radio Systems

How to Build a Wooden Planter

This “Junk” Cabinet Had $50 Worth of Lumber Inside!

Hexagonal Planter Design Tutorial | Fusion 360

Implementing Mixers in FPGAs: A Software-Defined Radio Essential

How to Make Giant Wooden Dice | A Fun Woodworking Project From Reclaimed Wood

How to determine How fast your FPGA is

Avoiding Glitches in Xilinx FPGA Designs — Clocks, Data, and Resets Explained

ISERDESE3 Xilinx Deserializer – UltraScale & UltraScale+ SERDES Block Explained

Clock Generation in FPGAs Part 1: Good and Bad Clock Divider Design

How Vivado Detects Unsafe Clock Domain Crossings — Live Demo

How I Lost 19 Pounds in 8 Weeks on the Mayo Clinic Diet | Dr. Paul Kerstetter

🔧 Bit Alignment & Bit Slipping in FPGAs Explained | ISERDESE2 Tutorial (Xilinx Series 7)

Using ISERDESE2 (Serdes) in Xilinx FPGA's with Vivado

The Mayo Clinic Diet : Week 5

The Mayo Clinic Diet: Week 1

FPGA Timing Closure with Clock Wizard in Vivado– Practical Example on ZCU104

FIR Filters on FPGAs: Timing Closure with VHDL & Verilog

Understanding Reset Strategies in FPGA Design | VHDL & Verilog Examples

Rainbow Trout Fishing in Curt Gowdy State Park | Kayak Adventure

Life as an Engineer with a Ph.D. — Was It Worth It?

Life as an Engineer at Work – What It’s Really Like

Day 3 of My Chevy Tahoe Camper Conversion Adventure!

Old Faithful Eruption & Scenic Hike | Chevy Tahoe Camper Conversion Adventure

What No One Tells You About Self-Publishing on Amazon KDP

My First Month on KDP: What I Learned (Publishing a Book for FREE)

Camping Off-Grid in Yellowstone | Chevy Tahoe Camper Conversion Adventure

Exploring Wyoming in My Chevy Tahoe Conversion | Thermopolis Hot Springs Adventure

From Thermopolis to Yellowstone in My Chevy Tahoe Camper Conversion

Spending My First Night in a Chevy Tahoe Conversion | Thermopolis, WY

Understanding SWOT Analysis: A Simple Breakdown with Real Company Examples

Fishing Adventure at Curt Gowdy State Park, Wyoming

Relaxing Kayaking at Samson Island | Satellite Beach, Florida

The Worst GDP Drop in U.S. History — Explained!

Mastering the Market: How I Made $40,000 in 6 Months

The Power of Letting Go (And Why It’s Smarter Than You Think)

The Secret to Setting Goals You’ll Actually Enjoy

Why Smaller Goals Might Be the Key to Bigger Success