The I2C Protocol

FPGA vs ASIC

System on Chip (SOC)

fpga design flow

Common design mistakes: READ WRITE RACE IN VERILOG

APB PROTOCOL

The Multi cycle Path in VLSI

Concept of False Path

Clock Skew and Jitter

Parity Generator

FIFO DEPTH CALCULATIONS

An Introduction to FIFO

Clock Generation Code Using Verilog | Comprehensive Tutorial

Lint in RTL Design || RTL Linting || Linters

Function and Task in Verilog.Difference between the Function and Task

Synthesizable Constructs in VLSI

Implementation of Logic Gates using MUX

Mastering Timing Closure in VLSI: Unleashing Design PerformanceTiming Closure in VLSI TimingAnalysis

Clock Skew in VLSI.Impact of Clock Skew.

Most Frequently asked Interview questions for RTL Design Engineer

Hold Time in VLSI. How to fix hold time violation.

Setup Time in VLSI.. Setup and hold time of flipflops explained . how to fix setup violations..

SRAM (Static Random Access Memory)with verilog code.Difference between SRAM and DRAM types of RAM

Quartus Prime tutorial for beginners.. how to use Quartus prime lite edition..

How to use ModelSim from Scratch for simulating a verilog code for Half Adder

How to use xilinx Vivado tool.

SERIAL IN SERIAL OUT Shift Register Verilog code using Xilinx Vivado tool

D Flip Flop."Demystifying the D Flip-Flop: Unleashing the Power of Digital Circuits"

VLSI GYAN INTRO

Scratch Programming

Decimal to Hexadecimal conversion

Decimal to Binary Conversion

Decimal to octal conversion

Switching Theory And Logic Design Course: Number System