TMS9x18 VDP Status Register Polling Demonstration

Z80 Nouveau Sprites FSM pt. 3

Z80 Nouveau Sprites FSM pt. 2

Z80 Nouveau Sprites FSM pt. 1

Z80 Nouveau Sprites Overview

Z80 Nouveau Joystick Port

Cheap Amazon Hackable Joystick from FOSA

FPGA #31 - Comments in an iverilog $readmemh() Hex File

FPGA #30 - The __FILE__ Macro

Z80 Nouveau vdp_fsm.v Module Walkthrough pt. 1

Z80 Nouveau vgasync.v Module Walkthrough

Box Opening A JCFANTS GJ-150 Miter Gauge & Testing On A 5+ Decades Old, Rusty, Craftsman Table Saw

Z80 Nouveau vram.v Module Walkthrough

FPGA #29 - VGA/RGB Video Resistor DAC With a Color Palette.

FPGA #28 - A Serial CRC Generator Module And a Verilog Generate For loop Example

Using Grok to Develop a Modbus Application

Z80 Nouveau vdp_reg_ifce.v Module Walkthrough

Z80 Nouveau vdp_irq.v Module Walkthrough

Z80 Nouveau vdp99.v Module Walkthrough

Z80 Nouveau CPU & VDP Bus Custom Clock Domain Synchronization

Z80 Nouveau VDP99 Overview

FPGA #28 - Creating a Verilog Testbench from a Waveform Diagram

Z80 Nouveau VGA Proof Of Concept

FPGA #27 - Using a pulse stretcher in a clock domain crossing synchronizer

FPGA #26 - A closer look at the ICE40HX Block RAMs

FPGA #25 - Verilog Custom Signal Synchronizers

FPGA #24 - ICE40HX PLL

8080 and Z80 Assembly Language

A simple DIY Solder Dispenser

Western Electric 108AA Loudspeaker Teardown

FPGA #23 - Switch Debouncing

FPGA #22 - Clock Domains, Metastability, and Synchronizers

FPGA #21 - Verilog Bidirectional Open-Collector Drivers

FPGA #20 - Verilog Tristate Drivers and the ICE40 SB_IO Module.

Simple PS/2 Keyboard Interface in Verilog

VGA Sync Generator and Color Bars in Verilog

An Introduction to VGA Signal Timing

Z80 Retro #74 - 3D Printed Stackable PCB Standoffs

Z80 Nouveau Peripheral Shopping

Opti-Tekscope Digital USB Microscope Camera Unboxing and Linux Testing

Z8S180, ICE40HX CP/M BIOS Port Public Release

Z8S180, ICE40HX CP/M BIOS Port Part 4

Z8S180, ICE40HX CP/M BIOS Port Part 3

Z8S180, ICE40HX CP/M BIOS Port Part 2

Z8S180, ICE40HX CP/M BIOS Port Part 1

FPGA #19 - A look at the iCE40 Technology Library

FPGA #18 - Verilog Finite State Machines Part 2

FPGA #17 - Verilog Finite State Machines Part 1

FPGA #16 - Verilog case, casez, and casex

FPGA #15 - Verilog Modules, Parameters, and Localparams

FPGA #14 - Verilog Always Pt. III (Synthesizable Design Patterns)

FPGA #13 - Verilog Always Pt. II (Nonblocking Assignments)

FPGA #12 - Verilog Always Pt. I (Combinational Circuits)

Z8S180 Breakout Board Testing Pt. III

Z8S180 Breakout Board Testing Pt. II

Z8S180 Breakout Board Testing Pt. I

Z8S180 Breakout Board Assembly

FPGA #11 - Priority Routing Network

FPGA #10 - Verilog == and === operators

FPGA #9 - Verilog Vectors & Arrays