Xilinx DPU End‑to‑End FPGA Deployment (by Mukesh Narayana, PhD Candidate, BITS Goa)

AM Modulator Part-1

Ethernet with Standalone

Histogram Equalization IP

Hardware Software CoDesign with Vivado and Vitis

Xillinx Vitis Introduction| Hello World with Vitis

Quartus|Synthesis Part-1|Part-25

Verilog Implementation of Synchronous Circuits | Quartus | Part24

Good Coding Style for Embedded Systems |Interrupt Service Routines| Call back functions| Part-2

LPC2378|Interrupt Controller|Writing ISRs

FPGA Implementation of Verilog Code|Quartus|Part23

LPC2378|DAC|Generating Sine wave using microcontroller

LPC 2378|ADC|Burst Mode

LPC 2378|ADC|Software Controlled Hardware Triggered mode

LPC 2378|ADC|Software Controlled Software Triggered mode

Good Coding Style for Embedded Systems| Part-1

LPC2378|Timer|MATCH Mode

LPC2378|Timer|Input capture

LPC2378|Timer|Free running Counter

LPC2378|Timer|Free running timer

LPC2378|GPIO|Interrupts

LPC2378|GPIO|Enhanced (Fast) Mode

LPC2378|GPIO|Legacy Mode

Design of Testbenches Part 2| Reading and Writing from text files| Signal Monitoring Part - 22

Modelling of Memory Part-3| Modelling Synchronous FIFO|Verilog|Part 26

Modelling of Memory Part-2| Modelling Read Only Memory (ROM)|Verilog| Part 25

Modelling of Memory Part-1| Modelling Random Access Memory (RAM)|Verilog| Part 24

Logic Values| Multiple drive|Verilog|Part 23

Design of Testbenches Part 1| Generating Clocks| Initial Block| Signal Monitoring Part - 22

Design of Counters | Part - 21

Design of a Simple Piano | Declaring Constants in Verilog | Module Parameterization | Part - 20

Design of Timers | Measurement of Wall clock time | Part - 19

Design of Encoders and Decoders | Physical implementation of if else if condition | Part 18

Behavioral Modeling of Combinational Circuits | Latch Inference | Part 17

Blocking vs Non-blocking Assignment Statements | Part-16

General Structure of Synchronous Circuits| Behavioral Modeling of Synchronous Circuits| Part-15

Asynchronous Reset and Preset| Behavioral Modeling| Limitations of Modeling| Part 14

Behavioral Modeling | Synchronous and Asynchronous Resets | Part 13

Behavioral Modeling | Modeling a Flip flop | Sequential Circuits | Part 12

Logical Operators|Implementation of Comparators and Multiplexer|Part 11

Multiplication, Division and Modulus Operations|Part 10

Signed and Unsigned Addition in Verilog|System Functions|Part 9

Assignment, Concatenation and Bitwidth mismatch| Verilog Operators| Part 8

From Verilog to Chips|Part 7

Operators in Verilog 1|Bit-wise Operators|Part 6

Simulation of Adder|ModelSim scripting|Part 5

Hierarchical Design in Verilog|Instantiations|Verilog|Part 4

Simulation Basics|Modelsim|Part-3

First code in Verilog|Module and Port Declarations|Gate Models|Verilog| Part 2

Introduction to Hardware Description Languages| Verilog HDL | Part 1

Network on Chip (NoC) with FPGAs|Part 2|Design of a Torus NoC

Sending email from Lambda Function

Network on Chip (NoC) with FPGAs|Part 1|Introduction

Video Interfacing with Zynq (FPGAs): Part 7 Interfacing ZedBoard with HDMI Monitor

Storing processed data in DynamoDB from AWS Lambda

Vivado for FPGA design: Part 1 Installation and licensing

Triggering AWS Lambda from AWS IoT

What is AWS Lambda? Introduction, Configuration and Testing

Connecting ZedBoard with Wifi. Controlling Peripherals Programmatically Part 3

Connecting ZedBoard with Wifi. Controlling Peripherals Part 2