Physical Verification LVS | PEX | Post-layout Simulation using Verilog netlist

Part 1: Common Source Amplifier Design using SCL 180nm

IINVENTIVE 2026

NIT Silchar VLSI Lab Tour

Bharat Innovates 2026|NIT Silchar Project Proposal

A brief session on Analog IC design ISchematic to Chip Tapeout at Siliguri Institute of Technology

Neural Amplifier Design as a part of MeitY Funded SMDP C2SD Project | R&D Fair IInventive 2025

Part 3: Layout of Differential Amplifier using gpdk90nm | Post Layout Simulation

Part 1: How to Design Differential amplifier using GPDK90nm Technology

Part 2 : How to Design Practical Differential Amplifier using gpdk90nm Technology

How to find process parameter of any technology node | UMC180| Cadence

Two Stage Op-amp design | AC Analysis | DC Analysis | PSRR | CMRR | ICMR | Noise | using TSMC65nm

How To Find Channel Length Modulation Coefficient Lambda using MOS Output Characteristics

Tutorial 2: Universal Logic Gates Design and simulation using LTSpice | NAND Gate| NOR Gate

Tutorial 1: CMOS inverter Design & Simulation using LTspice |VTC | Transient Analysis

Part 4: Two-Stage Op-amp Layout verification and Post-Layout simulation | DRC | LVS | PEX| ASSURA

Part 3. Layout of Two stage Opamp | UMC180nm Technology

Part 2: Simulation and analysis of 2-stage op-amp | PSRR | SLEW RATE | ICMR | POWER

Part 1: Analog Circuit Sizing using Softcomputing Algorithm | AC Analysis | Gain | Phase | CMRR

Current Mirror Layout using TSMC65nm Technology with interdigitation matching.

Verilog Coding and Simulation in Cadence Virtuoso Analog Environment | AMS Simulation

Differential Pair Layout using Common Centroid Matching Technique in TSMC 65nm PDK

PART 2: Logical Equivalence Check (LEC) using Cadence Conformal Tool

Standard Cell Layout Using Euler Path Optimisation demonstrated in Cadence Virtuoso.

PART 1: RTL SYNTHESIS USING CADENCE GENUS TOOL

Tools required for digital IC Design flow

Part 2: FPGA IN LOOP | VIO | ILA | SLICE IP CORE | BLOCK IMPLEMENTATION

Part 1: NEXYS 4 DDR FPGA IMPLEMENTATION

Analog Mixed Signal IC Design: LEF File Generation using Cadence Abstract Tool Tutorial

Analog IC Design Flow: Essential Tools and Workflow

Analog Layout basics

Part 2: TSMC65nm Technology Layout | CMOS inverter Layout | Cadence Virtuoso

Part 1: CMOS Inverters Made Easy with Cadence Virtuoso in TSMC65nm Tech!

From Idea to Reality: How Schematic Design is Turned into a Chip Using SCL180nm Technology

Xilinx ISE 14.7 Tutorial

Cadence Video Lecture

FPGA Based Scanning & positioning system