Crowded Vias in Your PCB Design? Double-Check for EMI Control
This is one of those issues that looks innocent at first, but in many cases, it’s not.
So, what’s happening here?
The designer of this board routed the differential pairs and added Return Reference Vias (RRVs) to contain the EM fields of the signal during vertical propagation, in other words, when going from one layer to another in the stackup.
That’s great! It’s already one of those nice touches that can prevent big EMC failures later on.
But here’s the catch: by applying this technique, the via placement became a bit crowded near the differential pair vias.
Since these vias are connected to the Return and Reference Plane (RRP), when we analyze that plane everything looks fine.
However, if we look at the other plane, in this case the power plane, which is not connected to these vias or to the differential pair vias, we find that a large hole has been created in the plane.
Why is this a problem?
One issue with this large gap is that current cannot flow directly through this portion of the plane. Because of the hole, the current is forced to detour and find another path to its destination.
Detours create two potential problems:
- They can increase the size of the current loop. A larger enclosed loop area often means higher emissions.
- The current is forced away from its preferred path, which can bring it closer to other signal traces, increasing the risk of crosstalk with other nets.
A quick fix is to keep using RRVs, but space the vias properly so that the plane remains more continuous. Smaller holes mean more copper area for the current to flow through.
This simple step can save you from a costly board respin caused by EMI or signal integrity issues.
To electromagnetic enlightenment,
Dario
P.S. If you’re still unsure how to put these concepts into practice and are serious about mastering EMI control, join my free crash course here: fresuelectronics.com/
Dario Fresu
Crowded Vias in Your PCB Design? Double-Check for EMI Control
This is one of those issues that looks innocent at first, but in many cases, it’s not.
So, what’s happening here?
The designer of this board routed the differential pairs and added Return Reference Vias (RRVs) to contain the EM fields of the signal during vertical propagation, in other words, when going from one layer to another in the stackup.
That’s great! It’s already one of those nice touches that can prevent big EMC failures later on.
But here’s the catch: by applying this technique, the via placement became a bit crowded near the differential pair vias.
Since these vias are connected to the Return and Reference Plane (RRP), when we analyze that plane everything looks fine.
However, if we look at the other plane, in this case the power plane, which is not connected to these vias or to the differential pair vias, we find that a large hole has been created in the plane.
Why is this a problem?
One issue with this large gap is that current cannot flow directly through this portion of the plane. Because of the hole, the current is forced to detour and find another path to its destination.
Detours create two potential problems:
- They can increase the size of the current loop. A larger enclosed loop area often means higher emissions.
- The current is forced away from its preferred path, which can bring it closer to other signal traces, increasing the risk of crosstalk with other nets.
A quick fix is to keep using RRVs, but space the vias properly so that the plane remains more continuous. Smaller holes mean more copper area for the current to flow through.
This simple step can save you from a costly board respin caused by EMI or signal integrity issues.
To electromagnetic enlightenment,
Dario
P.S. If you’re still unsure how to put these concepts into practice and are serious about mastering EMI control, join my free crash course here: fresuelectronics.com/
*Qualifications apply.
2 weeks ago | [YT] | 12