13:40
L-1.1: Computer Organization and Architecture Syllabus Discussion for GATE and UGC NTA NET
Gate Smashers
9:40
L-1.2: Von Neumann's Architecture | Stored Memory Concept in Computer Architecture
15:11
L-1.3:Various General Purpose Registers in Computer Organization and Architecture
7:59
L-1.4:Types of Buses (Address, Data and Control) in Computer Organization and Architecture
11:26
L-1.5: Common bus system using multiplexer | Computer organization and Architecture
19:11
L-1.6: Common Bus system| How basic computer works
5:11
L-1.7: Types of Instructions in General Purpose Computer | Computer Organization and Architecture
7:45
L-1.8: Data Transfer Instructions in Computer Organisation and Architecture
8:44
L-1.9: Arithmetic Instructions(Data Manipulation) in Computer Organisation and Architecture
9:12
L-1.10: Logical Instructions(Data Manipulation) in Computer Organisation and Architecture
13:28
L-1.11: Shift Instructions(Data Manipulation) in Computer Organisation and Architecture
10:51
L-1.12: Program Control Instructions(Types of Control Instructions) | Computer Organization
10:40
L-1.13: What is Instruction Format | Understand Computer Organisation with Simple Story
8:51
L-1.14: Question on Instruction Format | Computer Organization | UGC NTA NET June 2021
8:03
L-1.15: Single Accumulator CPU Organisation | Single Address Instructions in Computer Organisation
7:19
L-1.16: General Register CPU Organisation | Two and Three Address Instructions | COA
11:50
L-1.17: Register Stack Organisation | Zero Address Instructions | COA
6:03
L-1.18:Memory Stack Organisation | Memory stack Vs Register stack | COA
11:45
L-2.1: What is Addressing Mode | Various Types of Addressing Modes | COA
4:56
L-2.2: Implied Addressing Mode | Computer Organisation and Architecture
6:36
L-2.3: Immediate Addressing Mode | Computer Organisation and Architecture
4:39
L-2.4: Register Mode | Addressing Mode | Computer Organisation and Architecture
6:22
L-2.5: Register Indirect Mode | Addressing Modes | Computer Organisation and Architecture
6:51
L-2.6: Auto Increment and Decrement Addressing Modes | Computer Organisation and Architecture
4:51
L-2.7: Direct Addressing Mode || Computer Organisation and Architecture
6:05
L-2.8: Indirect Addressing Mode | Computer Organisation and Architecture
7:08
L-2.9: Relative Addressing Mode || Computer Organisation and Architecture
6:58
L-2.10: Base Register Addressing Mode || Computer Organisation and Architecture
4:05
L-2.11: Indexed Addressing Mode || Computer Organisation and Architecture
4:46
L-2.12: Question on Addressing Modes | Computer Organization | UGC NTA NET 2021
7:32
L-3.1: Memory Hierarchy in Computer Architecture | Access time, Speed, Size, Cost | All Imp Points
10:04
L-3.2: Independent vs Hierarchical Memory Organization | 2-Level Memory Organization
8:19
L-3.3: 3-Level Memory Organisation || Computer Organisation and Architecture
5:50
L-3.4: GATE 2004 Question on 3-Level Memory Organisation || Computer Organisation and Architecture
7:40
L-3.5: What is Cache Mapping || Cache Mapping techniques || Computer Organisation and Architecture
22:03
L-3.6: Direct Mapping with Example in Hindi | Cache Mapping | Computer Organisation and Architecture
7:22
L-3.7: GATE 2005 Question on Direct Mapping | Cache Mapping Questions | Computer Organisation
9:56
L-3.8: Fully Associative Mapping with examples in Hindi | Cache Mapping | Computer Organisation
9:08
L-3.9: Advantages and Disadvantages of Direct Mapping | Cache Mapping | Computer Organisation
10:52
L-3.10: Set Associative Mapping with Examples in Hindi | Cache Mapping | Computer Organisation
8:47
L-3.11: Locality of Reference in Cache Memory | Spatial Vs Temporal Locality | Computer Organisation
5:35
L-3.12: Cache Replacement Algorithms in Computer Organisation and Architecture
8:58
L-3.13: LRU (Least Recently Used) Cache Replacement Algorithm | Computer Organisation & Architecture
8:16
L-3.14: Gate 2014 Question on Set Associative Cache Mapping | Computer Organisation and Architecture
9:05
L-3.15: FIFO Cache Replacement Policy with example | Computer Organisation and Architecture
7:31
L-3.16: LRU(least recently used ) Cache Replacement Policy | Computer Organisation and Architecture
8:18
L-4.1: Pipelining with real life example| Need of Pipelining | COA
3:54
L-4.2: Pipelining Introduction and structure | Computer Organisation
13:04
L-4.3: Pipelining Vs Non-Pipelining | Instruction Execution | Speedup, Efficiency, Utilization | COA
10:54
L-4.4: Stage Delay in Pipeline | Previous Year GATE Question | Computer Organisation & Architecture
4:25
L-4.5: Numerical Question on Pipelining | Previous year GATE Question | COA
10:29
L-4.6: What is Hazard in Pipelining | various types of Hazards | computer Architecture
9:33
L-4.7: Structural Hazards in Pipelining | Types of Hazards with Example in Hindi
13:52
L-4.8: Control Hazards in Pipelining | Types of Hazards with Example in Hindi
8:05
L-4.9: What is Read After Write(RAW) Hazards| Data Hazard in Pipelining with Example in Hindi | COA
9:19
L-4.10: Write After Read Hazard with Example|Data Hazards| Computer Organisation and Architecture
5:51
L-4.11: Write After Write Hazard | Data Hazards in Pipelining | Computer Organization &&Architecture
Register Renaming in Computer Organization | Data Hazard
5:45
I/O Interface in Computer Organization
9:37
Interrupts in 8085 microprocessor | Types of Interrupts in Computer Organization
6:35
Daisy Chaining in Priority Interrupt | Priority Based Interrupt in I/O Organization
7:38
Parallel priority interrupt | I/O organization
8:49
Question on Interrupt Handling(I/O organization) | Computer Organization | UGC NTA NET June 2021
7:01
Question on DMA (Direct Memory Access) | Input/Output Organization| COA | UGC NTA NET June 2021
8:22
RISC vs CISC | Computer Organization & Architecture
11:11
Operand Forwarding in Computer Organization & Architecture | Data Hazard
