Digital Design Lab 1: LTSpice Tutorial - 7400 Series TTL Gates | Spice Model

Digital Design Lecture 1: Introduction to Digital Systems

Digital Design Lecture 2: Number System Part 1

Digital Design Lab 3 : Four-bit Adder and BCD Adder with LT Spice using 74XX Series TTL Gates

Digital Design Lab-2: Parity Gen and Adders with LT Spice uising 74XX Series TTL Gates

Digital Design Lecture 3: Number System Part 2

Digital Design Lecture 4 Boolean Algebra

Digital Design : Doubt Class 1

Digital Design Lecture 5 Two &Three Variable K maps

Introduction to Verilog and Implementation of Majority Circuit in Xilinx ISE

Digital Design Lecture 6 : Four Variable K Maps

Digital Design Tutorial 2 Boolean Algebra & Logic Gates

Digital Design Lecture 7 : Logic Gate Realization and Design

Digital Design Lecture 8 : Five Variable K-map

Digital Design Tutorial 4 : K maps

Simplification of Function using Quine McCluskey Algorithm

Static Hazards in Digital Circuits and Optimization of Multi-Output Digital Circuits

Digital Design Tut 4: Simplification of Function using Quine McCluskey algorithm

Arithmetic Circuits, Half adder, Full Adder, Ripple Carry & Carry Look-Ahead Adder

Data flow modelling, Verilog Implementation of Half Adder and Full Adder in Xilinx ISE

Data flow modelling in Verilog and Implementation of BCD Adder in Xilinx ISE

4 Bit Binary Ripple Carry and Carry Look Ahead Adders , Array Multipliers and Magnitude Comparators

Real-Life Examples of Combinational Circuit Design using K map

Encoder and Decoder Design with Real- life examples

Multiplexers and Demultiplexers, Design and Implementation of Logic Circuits using Mux

Sequential Circuits, SR latches, and SR NOR latches, S'R' Nand Latches, SR with Enable Latches

Problems and Solutions Hazards, Decoder and Encoders

D Latches and D Flipflops

JK Flipflops and T Flipflops and Design of JK and T flipflops using D Flipflops

Decoder & Mux based design in LT Spice, Full Adder using Decoder, Full adder using Mux and Decoders

Sequential Circuit Design using D Flipflop, JK Flipflop, 2 bit counter, mod-3 and asynchronous

Sequential Circuit Design in LT Spice with 7474 D flip flop and 74107 JK flip flop. Counter Design.

Operation and Timing Diagram of Latches D, JK Flipflops

Sequence Detector using D & J K flipflops, Overlapping & non-Overlapping Sequence, State Diagram.

Revision for Digital Design T2

State Table Reduction and Implication Table Reduction

Demonstration of 74XX series IC based Experiments on Digital Trainer Kit

Doubt Class II for DD T2 Exam

Sequential Circuit Design, Mod 5 Counter, Mod 6 Counter, Mod-10 Counter, Pre-settable Counter

Sequential Circuit Design, D Latch, D flip-flop, JK flip-flop, Counter design, Verilog in Xilinx.

Design of Asynchronous Counters, Ripple Counter ,Mod 4 Counter, BCD Counter, Multi-digit BCD Counter

Sequence Detector using D and JK flip flops

Synchronous Counters, BCD Counter, Ripple Counter, Johnson Counter

Applications of Counters, Serial Adder, ADC, Voltmeter, Frequency Meter, Stepper Motor Control

ROM, PROM, EPOM, EEPROM and Programming the ROM

State Table Reduction, State Chart Reduction, State row reduction, Implication table reduction

PLD PAL PLA SPLD CPLD FPGA

PLC, AOI, OA, Implementation of Boolean function using CMOS Transistors

Implementation of Functions using PROM, PLA and PAL

Sequential Binary Multiplier

Logic Function Implementation with CMOS devices

Booth Multiplier

Number System Part 2

Binary Codes