30:29
Conversion from Decimal Numbers to HEX, Binary, Octal in Digital Logic Design
EE-Vibes (Electrical Engineering Lessons)
4:10
2's Complement of a Number | Digital Logic Design | 2's Complement Example
22:22
Complement of a Number in Base r | Digital Logic Design
28:23
Canonical Forms of Boolean Functions | SOP | POS | Minterms | Maxterms in Digital Logic Design
27:01
Simplification of Boolean Functions using Karnaugh Map | K-map in Digital Logic Design
30:10
Design of Adder and Subtractor Circuits in Digital Logic Design (Half and Full Adder Subtractor)
28:24
How to Design a Magnitude Comparator in Digital Logic Design? 1-bit, 2-bit, 3-bit, n-bit Comparator
12:03
Working of 4 bit Adder Subtractor Circuit in Digital Logic Design #eevibessite #eevibes #eevibessite
9:24
Overflow in 4 bit Adder-Subtractor Circuit || Explanation with Example
3:14
Simplify the Boolean Expressions up to the given number of literals
3:54
Simplification of Boolean Function up to Given Number of Literals
5:00
Simplification of Boolean Function up to Given Number of Literals in Digital Logic Design
12:06
Prime Implicants and Essential Prime Implicants in Digital Logic Design|| Solved Example
5:22
Write the following Boolean expression in product of sums form | F=a'b+a'c'+abc
9:59
How to Perform BCD to Gray Code Conversion in Digital Logic Design?
6:14
Simplification of Boolean Function with K-Map using Don't Care Conditions in Digital Logic Design
14:10
How to Design an Even Parity and Odd Parity Generator and Detector Circuit in Digital Logic Design?
11:19
Design a 4-bit Circuit that takes the 2's Complement using XOR Gates in Digital Logic Design
12:41
Find the minterms of the Boolean expressions by first plotting each function in a map
9:03
SOP and POS Representation of a Given Function in Digital Logic Design
7:59
Design of 4-to-2 Line Encoder Circuits in Digital Logic Design
13:43
Design of 4 to 2 Line Priority Encoder Circuit in Digital Logic Design
8:40
Working of SR Latch using NAND and NOR Gate in Digital Logic Design
10:25
Working of SR Latch using NAND Gates in Digital Logic Design
5:53
Working of D Latch
12:25
Working of Edge-Triggered D Flip Flop
6:20
Implementation of Boolean Function Using Mux (Multiplexer)
4:21
Flip Flop Timing Diagram: Setup Time, Hold Time and Propagation Delay
10:05
How to Implement following Boolean function using multiplexer F(A, B, C, D)= Σ (0,2, 5, 8, 10, 14)
12:45
Analysis of Sequential Circuit Using D Flip Flop
8:53
How to Draw the State Diagram for a Sequential Circuit?
16:02
Analysis of Sequential Circuit Using JK flip-flop
12:57
How to Design a sequential Circuit that Detects Three or More Consecutive 1's in the Input String?
13:09
5.6 A sequential circuit with two D flip-flops A and B, two inputs, x and y ; and one output z
5:55
5.7 A sequential circuit has one flip-flop Q, two inputs x and y, and one output S .
7:26
Shift Registers in Digital Electronics
7:28
D flip flop Vs D latch
11:49
What are the Counters ? UP Counter Operation
How to Design a Digital Stopwatch? Digital Logic Design Project
7:43
Design of a 4-bit Arithmetic Logic Unit (ALU)-DLD Project
2:07
Digital Logic Design Project Person/Objects Counter
0:59
Working Of Light sensitive Circuit Using LDR| DLD Project
11:58
Roll number28,30,51 1
11:15
Derive the state table and the state diagram of the sequential circuit
8:43
Depletion/ Enhancement CMOS for Low Power Family of Three-Valued Logic Design
5:57
Design of Analog to Digital Converter Using CMOS Logic
17:13
A sequential circuit has two JK flip-flops A and B and one input x . The circuit is described by the
7:09
How to Design a 4 to 1 line Multiplexer (MUX) by Using 2 to 1 Line Multiplexer?
8:51
Design a combinational circuit with three inputs, x , y , and z , and three outputs, A, B , and C .
4:30
A majority circuit is a combinational circuit whose output is equal to 1 if the input variables
4:07
Verilog Code for 3 input Majority Circuit with Test Bench Waveforms #verilog
8:26
Using a decoder and external gates, design the combinational circuit defined by the following
3:53
Timing Diagram of Simple D Flip Flop #flipflop #Dflipflop
11:36
Working of Serial-in and Parallel-out Shift Register || Step by step Explanation ||2024
7:38
Design a one-input, one-output serial 2’s complementer. The circuit accepts a string of bits
9:48
Design Steps for a Sequential Circuits| 2024 Easy Steps in Details
12:22
Design Sequential Circuit from State Diagram using Flip Flops and Combination Logic Gates
9:49
Design a Combinational Circuit that generates the 9's complement of a BCD digit.
7:01
Difference Between Combinational and Sequential Logic Circuits | DLD-2024 Short Questions
11:29
Design Steps for Combination Logic Circuits with Example| 2024
9:52
State Reduction Example in Digital Logic Design | Step-by-Step Explanation
9:29
Design a 4-to-1 Line multiplexer using only NAND gates | Solution
17:56
Design of 3 bit Up Counter using JK Flip Flop
20:28
Quine McCluskey Method in Digital Logic Design
1:01
BCD to Gray Code Converter Simple Explanation #shorts #reels #engineeringshorts #algorithms
9:01
Timing Diagram of JK Flip Flop | DLD Lecture
15:09
Binary Multiplier in Digital Logic Design | 2 bit, 3 bit Multiplier Explained
12:26
BCD Numbers and BCD Numbers Addition
0:51
Binary to Decimal Conversion #binarynumbers #decimalnumbers #shorts #reels #numbersystems
Decimal to Binary Conversion #decimalnumbers #shorts #reels #binarynumbers #engineering
Binary to Hexadecimal Conversion #binary #hexnumbers #shorts #reels
Today's Problem of DLD #MorrisManoSoluions #DLD #eevibes
1:55
Simplification of Boolean Function T2 using Boolean Algebra and K-Map #kmap #BooleanAlgebra #DLD
1:00
Consider the combinational circuit shown in Fig. P4.1 . (HDL—see Problem 4.49.)
Design of a 1 bit Magnitude Comparator
14:20
How to Design a Full Adder Circuit Using Only NAND gates ?
0:58
Implementation of XOR Gate using only NAND Gates
4:37
Combinational Circuit for Comparing Two 4-bit Binary Numbers
Most Common Logic Design Mistake | NAND vs NOR Explained
Half Adder Circuit Design Explained | Digital Logic Design Tutorial #education
11:34
Overflow of 8 bit Signed Numbers During Addition
Self Complementing Codes in Digital Logic Design | Explained with Examples
LIVE
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Implementation of Boolean Function using NAND Gates Only
0:57
SOP and POS Representation of Boolean Function
12:52
What are the Prime Implicants and Essential Prime Implicants?