Tejas Ketkar
I graduated from IIT Kanpur with a Bachelor’s and a Master’s of Technology in Electrical Engineering, earning two medals along the way. With over 7 years of experience in lifting weights under my belt, I've learned a ton about dedication and perseverance, which I now bring to my professional pursuits.
My channel is all about bridging the gap in the freely available information related to semiconductors, especially the things that often get overlooked. I've found that there's a lack of content for newcomers that goes beyond the basics and tackles more advanced concepts.
Here's what you can expect:
1. Engaging discussions on cutting-egde research papers
2. Clear illustrations of concepts that are often missed in traditional coursework
3. Insights from industry and academic leaders to help guide your journey
Thanks for stopping by and happy learning!
Tejas Ketkar
The ability to break down a seemingly complex circuit into smaller blocks can level up your circuit analysing capability.
On that note, let me post a simplified schematic of the current reference circuit from [1].
You might be familiar with M1-M4, M7 from my earlier videos/posts. If not, I’d encourage you to check out [2] and [3].
- What do you think the role of M5-M6 is?
- Do you think this circuit would require a startup circuit to function reliably?
[1]: ieeexplore.ieee.org/document/7527287
[2]: www.linkedin.com/posts/tejas-ketkar-568863167_anal…
[3]: https://youtu.be/JACTZqa-tY0?si=nUXry...
📡 Subscribe to the channel to stay updated with such content
#circuits #vlsi #icdesign
1 year ago | [YT] | 16
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Tejas Ketkar
*Circuits Puzzle*
- You are given a 1V DC voltage source. You need to generate a -1V DC signal from it. You can use any circuit components that you like, as per your creativity.
- Can you think of any application of such a problem (or a similar one)?
#circuits #puzzle #icdesign #hardware
1 year ago | [YT] | 9
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Tejas Ketkar
If you could ask anything to a circuit design professor at IIT, what would it be?
Subscribe to stay updated since a special video is coming out soon.
Besides that if you are interested in hearing about device modeling then check out my chat with Nilesh at:
https://youtu.be/kociXHyunfo?si=ctmQ8...
Happy Learning!
1 year ago | [YT] | 9
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Tejas Ketkar
A lot of folks have been reaching out to me with their doubts and requests for mentorship.
Although I do try to respond to each one, sometimes there isn’t enough time or bandwidth left [considering the wide range of projects (personal and professional) that I’m involved in].
So feel free to connect with me via the following link:
topmate.io/tejas_ketkar
A couple of people have already reached out and have given wonderful feedback.
If you guys have any video requests then feel free to comment it below as well. If I see any common requests, then I’d try to cover it with priority.
Happy Learning!
1 year ago | [YT] | 8
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Tejas Ketkar
Bias generating circuits are omnipresent in all ICs.
- Recently N. Raja Sekhar posted about a very nice concept (lnkd.in/gtarSY_F)
- In an attempt to drive his point home, I decided to share the following three variants with you, that might generate a VGS/R current.
- It would be instructive to identify the negative and positive feedback loops (if present)
- Which one would you prefer to use and why?
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#icdesign #bias #circuits #analog #semiconductor #semiconductors
1 year ago | [YT] | 18
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Tejas Ketkar
Why stop at a folded-cascode OTA when you can do more?
- What do you think might be the benefit of placing an N-Channel and a P-Channel differential input pair in parallel?
- If you thought about a few benefits, then can we use this kind of an input pair in other OTAs (5-transistor, telescopic cascode, etc) as well?
- Would this double the short-circuit transconductance (Gm)? If so, at what cost?
- Can you foresee any issues with such an input pair? Perhaps, the frequency compensation of OTAs utilising such input stages?
- Lastly, do you think that the benefits for such an input pair stay put for low supply voltages?
I hope pondering over these questions is an enlightening experience for you guys.
Keep an eye on the comment section, since folks much more wiser than me share their wisdom generously.
To stay updated with such content, check out:
lnkd.in/gdgZ6Er2
#icdesign #analog #circuits #semiconductors #hardware #interview #discussion
1 year ago | [YT] | 11
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Tejas Ketkar
What is the output impedance (Rout), in terms of the parameters associated with M1,M2,M3, and M4?
Is there any kind of feedback in this system?
1 year ago | [YT] | 17
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Tejas Ketkar
Drain Current Mismatch of a Current Mirror
- You’d commonly hear that the drain current mismatch of a current mirror can be lowered by increasing it’s overdrive voltage.
In fact, I discussed it in a video myself. To understand/revisit why that works, check out:
https://youtu.be/iCMGivONj-U
- Is there an alternate way?
- What if you bias the current mirror transistors in subthreshold/weak inversion, and degenerate them with resistors (Fig. 2)
- We can design the circuits in Fig. 1 and Fig. 2 to have the same minimum output voltage (Vout,min).
Which one (Fig. 1 or Fig. 2) do you think would have a better matching for the drain current, for the same area?
Which one would you prefer, and for what kinds of applications?
#circuits #vlsi #analog #semiconductors #icdesign #matching #layout
1 year ago (edited) | [YT] | 12
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Tejas Ketkar
In any circuit, the worst case occurs either in the strong (fast) or the weak (slow) corner.
Check out the comments for some interesting links and discussions.
#vlsi #hardware #analog #semiconductors #icdesign
1 year ago | [YT] | 3
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Tejas Ketkar
Connecting a resistance between the gate terminals of the current mirror transistors can impact it’s performance!
❓What would the output noise current be in the attached circuit?
- The diode-connected transistor, Mref, may impart significant flicker noise at the output. This issue can be mitigated by the addition of Rb and Cb, which would lower the bandwidth {1/[2*pi*(1/gm,ref +Rb)*Cb]} for the noise propagated from Mref to the output.
However, there are some salient points to it:
- Rb would contribute its own thermal noise
- Gate leakage flowing through Rb may create a DC offset
- Area trade-offs between Rb and Cb
- Current mirror pole may affect other performance metrics. For example, degrade the phase margin, if used in an OTA.
On another note, if you place Rb between the points marked ‘A’ and ‘B’, then you get another interesting application of this current mirror load. Any guesses?
If you wish to stay updated with such content, check out:
youtube.com/@tejasketkar?si=KocMQU33Klnb2_uM
#circuits #noise #vlsi #hardware #semiconductors
1 year ago | [YT] | 14
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