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Q8. Which parameter is primarily optimized during gate sizing?
17 minutes ago | [YT] | 0
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Q7. Which timing analysis mode assumes best-case process, highest voltage, and lowest temperature?
1 day ago | [YT] | 0
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Q6. What is the purpose of Engineering Change Order (ECO) cells in a standard-cell library?
2 days ago | [YT] | 1
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Q5. Which of the following is NOT considered a physical design stage?
3 days ago | [YT] | 2
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Q4. What is the primary function of a clock buffer?
4 days ago | [YT] | 2
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Q3. Which type of parasitic extraction provides the highest timing accuracy?
5 days ago | [YT] | 1
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Q2. Which file is primarily used by physical design tools to describe the abstract physical information of standard cells?
6 days ago | [YT] | 1
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Q1. Which optimization technique is primarily used to reduce the logic depth of a combinational circuit?
1 week ago | [YT] | 0
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Answers (21–31)
21. C
22. C
23. C
24. B
25. B
26. B
27. B
28. C
29. C
30. B
31. C
1 week ago | [YT] | 0
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Q31.Which of the following best describes timing closure in an ASIC project?
1 week ago | [YT] | 0
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