WHY-VLSI

Verilog is one of the important HDL language needed for professionals willing to enter into the field of VLSI. Apart from the different concepts, coding skill is also equally important.

But the best way to learn Verilog coding is to first start learn to code with the digital design blocks. Below are some of the mostly used blocks essential for coding.

[1] Verilog Code for D Flip Flop (FF) / T FF with Synchronous reset.

[2] Verilog Code for D FF / T FF with asynchronous reset.

[3] Multiplexer code using if..else / ternary operator / case statement and data flow modelling.

[4] Verilog code for Priority encoder ckt.

[5] Verilog code for BCD counter with load and up / down count.

[6] Verilog code to swap the contents of two register with and without using a temporary variable.

[7] Verilog Code for D latch with positive gate and asynchronous reset.

[8] Verilog code for tristate buffer.

[9] Verilog code for 8 bit SISO and SIPO shift register.

[10] Given a FSM sequence write a verilog code for overlapping and non overlapping sequence using both Mealy and Moore state machine.

[11] Verilog code for SP RAM with asynchronous and synchronous read.

[12] Verilog code for 8 bit input data Barrel shifter.

[13] Verilog code for memory controller and a Traffic light controller.

[14] Verilog Code for asynchronous and synchronous FIFO.

2 years ago | [YT] | 1

WHY-VLSI

Difference between Blocking and Nonblocking statements in Verilog:

1. A blocking statement is a one step process i.e evaluate the RHS of the expression and update the LHS without any delay while Nonblocking is a two step process i.e. a) Evaluate the RHS expression at the beginning of time step and b) Update the LHS at the end of time step.

2. Blocking statement are executed in the Active region of Verilog Stratified Event Queue while Evaluation of RHS of Nonblocking statement occurred in Active Region and updation of LHS side happen in NBA region.

3. A blocking statement will not block the execution of statement that are in parallel block,means it will execute sequentially while Nonblocking assignment allow scheduling of assignment that are executed in sequential block.

4. Blocking assignment always suffer from the problem of Race condition when the assignment happen to it from two process concurrently. While in Nonblocking statement,there is no such problem since the updated value is assigned after time step.
Lets take an example to illustrate the problem:-

Blocking:-
always @(posedge clk)
X = y;
always @(posedge clk)
y = x;

Anyone of the above always blocks can be executed in any order and instead of swapping the values both the register will get updated with the same value which is a race condition.

Nonblocking:-

always @(posedge clk)
x <= y;
always @(posedge clk)
y <= x;

5. While Modelling combinational logic,blocking statements are preferred while for sequential logic,nonblocking statements are always used.

6. Blocking statement can be used in initial, always blocks and assign statements while Nonblocking can only be used in initial and always block but assign statements can not be used.

2 years ago | [YT] | 2

WHY-VLSI

Synthesizable Construct in Verilog and efficient use of RTL coding required for those interested in VLSI:

To start with any HDL, it's important to segregate the constructs on the basis of Synthesizability because the constructs needs to be supported for RTL to convert it into netlist.

Following are the constructs which are categorised as synthesizable/non-synthesizable:

✓Synthesizable:
module, endmodule, always block, parameter, task(without any delay), function, assign, if..else, while loop, for loop, case, casex, casez, ports like input, output, input, forever loop, begin, end, instantiation, disable block, wire, reg, localparam, static arrays, blocking and nonblocking assignments, all the operators of verilog, compiler directives.

✓Non-synthesizable:
force and release, wait statement, delay, event control statement, deassign, initial, fork and join, time, tri0, tri1, udp's, pmos, nmos, rpmos, tranif0, tranif1, pull-up, pull down.

Some Basic Coding Guidelines:

1. Use of Blocking Statement in Combinational Circuits and use of Non blocking assignment in Sequential Circuits.

2. Mixing of Blocking and Non blocking statement should be avoided.

3. Delays should be avoided in RTL coding and execution of Inactive Region of the event queue.

4. Inference of Latches should be avoided.

Efficient use of RTL Coding:

✓ Use of enum instead of parameter.
✓ Use of always_ff, always_latch, always_comb instead of always.
✓ Use of unique and priority instead of full and parallel case.
✓ Proper use of Sensitivity list.

2 years ago | [YT] | 2