1. Logic Synthesis || VLSI Frontend to Backend series in Telugu

Alert !! VLSI Frontend to Backend || New series

Blocking and Non-blocking assignments || Verilog lectures in Telugu - 36

Continuous Assignment II Verilog lectures in Telugu - 35

Parallel Block Statements - Example with Fork-Join || Verilog lectures in Telugu - 34

Initial Block Example || Verilog lectures in Telugu - 33

Initial Block || Verilog lectures in Telugu - 32

4-bit Left Shift Register - sequential design || Verilog lectures in Telugu - 31

4:16 Decoder - sequential design || Verilog lectures in Telugu - 30

4:16 Decoder - combinational design || Verilog lectures in Telugu - 29

1:4 Demultiplexer - combinational design || Verilog lectures in Telugu - 27

Combinational Design - Full Adder || Verilog lectures in Telugu - 27

Combinational Design - Full Adder || Verilog lectures in Telugu - 25

Combinational Design - Half Adder || Verilog lectures in Telugu - 25

Always Block || Verilog lectures in Telugu - 23

Designing combinational & Sequential design using always block ||

Concatenation & Replication Operators ||Verilog lectures in Telugu - 22

Operators || Verilog lectures in Telugu - 21

Assign statements || Verilog lectures in Telugu - 20

Module Instantiation - Methods || Verilog lectures in Telugu - 19

Ports & It's types || Verilog lectures in Telugu - 18

Module & It's purpose || Verilog lectures in Telugu - 17

Memories in Verilog || Verilog lectures in Telugu - 16

Arrays & Array assignment || Verilog lectures in Telugu - 15

Bit-Select & Part-Select | Verilog lectures in Telugu - 14

Scalar & Vector | Verilog lectures in Telugu - 13

Examples for Data-Types || Verilog lectures in Telugu - 12

Integer, real, time, real time|| Verilog lectures in Telugu - 11

Identifiers & Keywords || Verilog lectures in Telugu - 7

Wire | Datatypes || Verilog lectures in Telugu - 9

Nets | Datatypes || Verilog lectures in Telugu - 9

Content of the variable & It's significance || Verilog lectures in Telugu - 8

Operators and Number Format || Verilog lectures in Telugu - 6

Comments & White spaces || Verilog lectures in Telugu - 5

Different Levels of Abstraction || Verilog lectures in Telugu - 4

Digital Design Methodologies || Top- Down & Bottom-up approach || Verilog lectures in Telugu - 3

FPGA Design Flow || Verilog lectures in Telugu - 2

VLSI Design Flow - ASIC || Verilog lectures in Telugu - 1

Switch statement || Java lectures in Telugu

Conditional Operators || Java lectures in Telugu

Operators || Java lectures in Telugu

Type Casting || Java lectures in Telugu

Data Types || Java lectures in Telugu

Variables || Java lectures in telugu

LVDT (linear variable differential transformer) in Telugu

Thermistor || Telugu

Transducer || Telugu

Transducer selection factors || Telugu

classification of transducers || Telugu

Schering's bridge || Telugu

Hays bridge || Telugu

Signal or Wave analyzers || Telugu

Maxwell Bridge || Telugu

AC Bridges || Telugu

Function generator || Telugu

Signal Generators || Telugu

Different types of CRO probes || Telugu

CRO probes || Telugu

Oscilloscope working principle || Telugu

Bidirectional and unidirectional elements || Telugu